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| viper100/sp viper100a/asp smps primary i.c. may 1999 block diagram type v dss i n r ds(on) viper100/sp 620v 3 a 2.5 w viper100a/asp 700v 3 a 2.8 w feature n adjustable switching frequency up to 200khz n current mode control n soft start and shut down control n automatic burst mode operation in stand-by condition able to meet oblue angelo norm (<1w total power consumption) n internally trimmed zener reference n undervoltage lock-out with hysteresis n integrated start-up supply n avalanche rugged n overtemperature protection n low stand-by current n adjustable current limitation description viper100 ? /100a, made using vipower m0 technology, combines on the same silicon chip a state-of-the-art pwm circuit together with an optimized high voltage avalanche rugged vertical power mosfet (620v or 700v / 3a). typical applications cover off line power supplies with a secondary power capability of 50w in wide range condition and 100w in single range or with doubler configuration. it is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components. powerso-10 1 10 pentawatt hv pentawatt hv (022y) f c 0 0 2 3 1 v dd osc comp drain source 13 v uvlo logic security latch pwm latch ff ff r/s s q s r1 r2 r3 q oscillator overtemp. detector error amplifier _ + 0.5 v + _ 1.7 m s delay 25 0 ns blanking current amplifier on/off 0.5v 1v/a _ + + _ 4.5 v ? 1/20
absolute maximum rating symbol parameter value unit v ds continuous drain-source voltage (tj = 25 to 125 o c) for viper100/sp for viper100a/asp -0.3 to 620 -0.3 to 700 v v i d maximum current internally limited a v dd supply voltage 0 to 15 v v osc voltage range input 0 to v dd v v comp voltage range input 0 to 5 v i comp maximum continuous current 2ma v esd electrostatic discharge (r = 1.5 k w c = 100pf) 4000 v i d(ar) avalanche drain-source current, repetitive or not-repetitive (t c =100 o c, pulse width limited by t j max, d <1%) for viper100/sp for viper100a/asp 2 1.4 a a p tot power dissipation at t c = 25 o c82w t j junction operating temperature internally limited o c t stg storage temperature -65 to 150 o c thermal data pentawatt-hv powerso-10(*) r thj-case thermal resistance junction-case max 1.4 1.4 o c/w r thj-amb. thermal resistance ambient-case max 60 50 o c/w (*) when mounted using the minimum recommended pad size on fr-4 board. current and voltage conventions - + 13v osc comp source drain vdd v comp v osc v dd v ds i comp i osc i dd i d fc00020 connection diagrams (top view) pentawatt hv pentawatt hv (022y) powerso-10 viper100/sp - viper100a/asp 2/20 pins functional description drain pin: integrated power mosfet drain pin. it provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. the device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, pcb stray inductance, and allowing a snubberless operation for low output power. source pin: power mosfet source pin. primary side circuit common ground connection. vdd pin : this pin provides two functions : - it corresponds to the low voltage supply of the control part of the circuit. if v dd goes below 8v, the start-up current source is activated and the output power mosfet is switched off until the v dd voltage reaches 11v. during this phase, the internal current consumption is reduced, the v dd pin is sourcing a current of about 2ma and the comp pin is shorted to ground. after that, the current source is shut down, and the device tries to start up by switching again. - this pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. in case of primary regulation, an internal 13v trimmed reference voltage is used to maintain v dd at 13v. for secondary regulation, a voltage between 8.5v and 12.5v will be put on v dd pin by transformer design, in order to stuck the output of the transconductance amplifier to the high state. the comp pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the v dd voltage, which cannot overpass 13v. the output voltage will be somewhat higher than the nominal one, but still under control. comp pin : this pin provides two functions : - it is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. its bandwidth can be easily adjusted to the needed value with usual components value. as stated above, secondary regulation configurations are also implemented through the comp pin. - when the comp voltage is going below 0.5v, the shut-down of the circuit occurs, with a zero duty cycle for the power mosfet. this feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever is the configuration) to provide a burst mode operation in case of negligible output power or open load condition. osc pin : an r t -c t network must be connected on that pin to define the switching frequency. note that despite the connection of r t to v dd ,no significant frequency change occurs for v dd varying from 8v to 15v. it provides also a synchronisation capability, when connected to an external frequency source. ordering numbers pentawatt hv pentawatt hv (022y) powerso-10 viper100 viper100a viper100 (022y) viper100a (022y) viper100sp VIPER100ASP viper100/sp - viper100a/asp 3/20 avalanche characteristics symbol parameter max value unit i d(a r) avalanche current, repetitive or not-repetitive (pulse width limited by t j max, d <1%) for viper100/sp for viper100a/asp (see fig.12) 2 1.4 a a e (ar) single pulse avalanche energy (starting t j =25 o c, i d =i d( ar) ) (see fig.12) 60 mj electrical characteristics (t j =25 o c, v dd = 13 v, unless otherwise specified) power section symbol parameter test conditions min. typ. max. unit bv dss drain-source voltage i d =1ma v comp =0v for viper100/sp for viper100a/asp (see fig.5) 620 700 v v i dss off-state drain current v comp =0v t j =125 o c v ds = 620 v for viper100/sp v ds = 700 v for viper100a/asp 1 1 ma ma r ds(on) static drain source on resistance i d =2a for viper100/sp for viper100a/asp i d =2a t j = 100 o c for viper100/sp for viper100a/asp 2.0 2.3 2.5 2.8 4.5 5.0 w w w w t f fall time id = 0.2 a v in =300v(1) (see fig.3) 100 ns t r rise time i d =2a v in = 300 v (1) (see fig. 3) 50 ns c oss output capacitance v ds = 25 v 150 pf (1) on inductive load, clamped. supply section symbol parameter test conditions min. typ. max. unit i ddch start-up charging current v dd =5v v ds =70v (see fig. 2 and fig. 15) -2 ma i dd0 operating supply current v dd =12v, f sw =0khz (see fig. 2) 12 16 ma i dd1 operating supply current v dd =12v, f sw = 100 khz 15.5 ma i dd2 operating supply current v dd =12v, f sw =200khz 19 ma v ddo ff undervoltage shutdown (see fig. 2) 8 v v ddo n undervoltage reset (see fig. 2) 11 12 v v ddhyst hysteresis start-up (see fig. 2) 2.4 3 v viper100/sp - viper100a/asp 4/20 electrical characteristics (continued) oscillator section symbol parameter test conditions min. typ. max. unit f sw oscillator frequency total variation r t = 8.2 k w c t =2.4 nf v dd = 9 to15 v with r t 1% c t 5% (see fig. 6 and fig. 9) 90 100 110 khz v oscih oscillator peak voltage 7.1 v v oscil oscillator valley voltage 3.7 v error amplifier section symbol parameter test conditions min. typ. max. unit v ddreg v dd regulation point i comp = 0 ma (see fig.1) 12.6 13 13.4 v d v ddreg total variation t j = 0 to 100 o c2% g bw unity gain bandwidth from input = v dd to output = v comp comp pin is open (see fig. 10) 150 khz a vol open loop voltage gain comp pin is open (see fig. 10) 45 52 db g m dc transconductance v comp = 2.5 v (see fig. 1) 1.1 1.5 1.9 ma/v v compl o output low level i comp =-400 m av dd =14v 0.2 v v comphi output high level i comp = 400 m av dd =12v 4.5 v i complo output low current capability v comp =2.5v v dd = 14 v -600 m a i comphi output high current capability v comp =2.5v v dd = 12 v 600 m a pwm comparator section symbol parameter test conditions min. typ. max. unit h id d v comp / d i dpeak v comp = 1 to 3 v 0.7 1 1.3 v/a v compoff v comp offset i dpeak =10ma 0.5 v i dpeak peak current limitation v dd =12v comppinopen 3 4 5.3 a t d current sense delay to turn-off i d = 1 a 250 ns t b blanking time 250 360 ns t on(min) minimum on time 350 ns shutdown and overtemperature section symbol parameter test conditions min. typ. max. unit v compth restart threshold (see fig. 4) 0.5 v t dissu disable set up time (see fig. 4) 1.7 5 m s t tsd thermal shutdown temperature (see fig. 8) 140 170 o c t hyst thermal shutdown hysteresis (see fig. 8) 40 o c viper100/sp - viper100a/asp 5/20 figure 1 :v dd regulation point i comp i comphi i complo v ddreg 0 v dd slope = gm in ma/v fc00150 figure 3 : transition time i d v ds t t tf tr 10% ipeak 10% v d 90% v d fc00160 figure 2 : undervoltage lockout v ddon i ddch i dd0 v dd v ddoff v ds =70v fsw = 0 i dd v ddhyst fc00170 figure 4 : shut down action vcomp vosc id t tdissu t t enable disable enable vcompth fc00060 figure 5 : breakdown voltage vs temperature figure 6 : typical frequency variation temperature ( c) fc00180 0 20 40 60 80 100 120 0.95 1 1.05 1.1 1.15 bv dss (normalized) temperature ( c) 0 20 40 60 80 100 120 140 -5 -4 -3 -2 -1 0 1 fc00190 (%) viper100/sp - viper100a/asp 6/20 figure 8 : overtemperature protection t t t t tj vdd id vcomp ttsd ttsd-thy st vddon vddoff sc10191 figure 7 : start-up waveforms viper100/sp - viper100a/asp 7/20 figure 9 : oscillator 1 2 3 5 10 20 30 50 30 50 100 200 300 500 1,000 rt (k w ) frequency (khz) oscillator frequency vs rt and ct ct = 1.5 nf ct = 2.7 nf ct = 4.7 nf ct = 10 nf fc00030 fc00030 1 2 3 5 10 20 30 50 0.5 0.6 0.7 0.8 0.9 1 rt (k w ) dmax maximum duty cycle vs rt fc00040 rt ct osc vdd ~360 w clk fc00050 for r t > 1.2 k w : f sw = 2.3 r t c t d max d max = 1 - 550 r t - 150 recommended d max values: 100khz: > 80% 200khz: > 70% viper100/sp - viper100a/asp 8/20 figure 10 : error amplifier frequency response 0.001 0.01 0.1 1 10 100 1,000 (20) 0 20 40 60 frequency (khz) voltage gain (db) rcomp = + rcomp = 270k rcomp = 82k rcomp = 27k rcomp = 12k fc00200 figure 11 : error amplifier phase response 0.001 0.01 0.1 1 10 100 1,000 (50) 0 50 100 150 200 frequency (khz) phase ( ) rcomp = + rcomp = 270k rcomp = 82k rcomp = 27k rcomp = 12k fc00210 viper100/sp - viper100a/asp 9/20 figure 12 : avalance test circuit fc00195 u1 viper100 13v osc comp source drain vd d - + 23 54 1 r3 100 r2 1k bt2 12v c1 47uf 16v q1 2 x sthv102fiin parallel r1 47 l1 1mh generator input 500us pulse bt1 0 to 20v viper100/sp - viper100a/asp 10/20 figure 13 : off line power supply with auxliary supply feedback ac in +vcc gnd f1 br1 d3 r9 c1 r7 c4 c2 tr2 r1 c3 d1 d2 c10 tr1 c9 c7 l2 r3 c6 c5 r2 u1 viper100 - + 13v osc comp source drain vdd fc00081 c11 figure 14 : off line power supply with optocoupler feedback fc00091 ac in f1 br1 d3 r9 c1 r7 c4 c2 tr2 r1 c3 d1 d2 c10 tr1 c9 c7 l2 +vcc gnd c8 c5 r2 u1 viper100 u2 r4 r5 iso1 r6 r3 c6 - + 13v osc comp source drain vdd c11 viper100/sp - viper100a/asp 11/20 operation description : current mode topology: the current mode control method, like the one integrated in the viper100/100a uses two control loops - an inner current control loop and an outer loop for voltage control. when the power mosfet output transistor is on, the inductor current (primary side of the transformer) is monitored with a sensefet technique and converted into a voltage v s proportional to this current. when v s reaches v comp (the amplified output voltage error) the power switch is switched off. thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. excellent open loop d.c. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. this results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. current mode topology also ensures good limitation in the case of short circuit. during a first phase the output current increases slowly following the dynamic of the regulation loop. then it reaches the maximum limitation current internally set and finally stops because the power supply on v dd is no longer correct. for specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the comp pin. an integrated blanking filter inhibits the pwm comparator output for a short time after the integrated power mosfet is switched on. this function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. stand-by mode stand-by operation in nearly open load condition automatically leads to a burst mode operation allowing voltage regulation on the secondary side. the transition from normal operation to burst mode operation happens for a power p stby given by : p stby = 1 2 l p i stby 2 f sw where: l p is the primary inductance of the transformer. f sw is the normal switching frequency. i stby is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. this current can be computed as : i stby = ( t b + t d ) v in l p t b +t d is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. note that p stby may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. as soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13v regulation level forcing the output voltage of the transconductance amplifier to low state (v comp used. it mixes a high performance compensation network together with a separate high value soft start capacitor. both soft start time and regulation loop bandwidth can be adjusted separately. if the device is intentionally shut down by putting the comp pin to ground, the device is also performing start-up cycles, and the v dd voltage is oscillating between v ddon and v ddoff . this voltage can be used for supplying external functions, provided that their consumption doesn't exceed 0.5ma. figure 17 shows a typical application of this function, with a latched shut down. once the oshutdowno signal has been activated, the device remains in the off state until the input voltage is removed. transconductance error amplifier the viper100/100a includes a transconductance error amplifier. transconductance gm is the change in output current (i comp ) versus change in input voltage (v dd ). thus: g m = ? i comp ? v dd the output impedance z comp at the output of this amplifier (comp pin) can be defined as: z comp = ? v comp ? i comp = 1 g m x ? v comp ? v dd this last equation shows that the open loop gain a vol can be related to g m and z comp : a vol =g m xz comp where g m value for viper100/100a is 1.5 ma/v typically. g m is well defined by specification, but z comp and therefore a vol are subject to large tolerances. an impedance z can be connected between the comp pin and ground in order to define more accurately the transfer function f of the error amplifier, according to the following equation, very similar to the one above: f (s) = gm x z(s) the error amplifier frequency response is reported in figure 10 for different values of a simple resistance connected on the comp pin. the unloaded transconductance error amplifier shows an internal z comp of about 330 k w . more complex impedance can be connected on the comp pin to achieve different compensation laws. a capacitor will provide an integrator function, thus eliminating the dc static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. this configuration is illustrated on figure 18. as shown in figure 18 an additional noise filtering capacitor of 2.2 nf is generally needed to avoid any high frequency interference. it can be also interesting to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. figure 19 shows such a configuration. note that r1 and c2 build the classical compensation network, and q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. external clock synchronization: the osc pin provides a synchronisation capability, when connected to an external frequency source. figure 20 shows one possible figure 17: latched shut down - + 13v osc comp source drain vdd viper100 shutdown u1 q1 q2 r1 r2 r3 r4 d1 fc00110 figure 16 : mixed soft start and compensation auxiliary winding - + 13v osc comp source drain vdd u1 viper 100 r1 c1 + c2 d1 r2 r3 d2 d3 + c3 fc00131 c4 viper100/sp - viper100a/asp 14/20 schematic to be adapted depending the specific needs. if the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. the optocoupler must be able to provide 20ma through the optotransistor. primary peak current limitation the primary i dpeak current and, as resulting effect, the output power can be limited using the simple circuit shown in figure 21. the circuit based on q1, r 1 and r 2 clamps the voltage on the comp pin in order to limit the primary peak current of the device to a value: i dpeak = v comp - 0.5 h id where: v comp = 0.6 x r 1 + r 2 r 2 the suggested value for r 1 +r 2 is in the range of 220k w . over-temperature protection: over-temperature protection is based on chip temperature sensing. the minimum junction temperature at which over-temperature cut-out occurs is 140 o c while the typical value is 170 o c. the device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40 o c below the shutdown value (see figure 8). figure 19 : slope compensation fc00141 - + 13v osc comp source drain vdd viper100 r1 r2 q1 c2 c1 r3 u1 c3 - + 13v osc comp source drain vdd viper100 u1 r1 c1 fc00121 c2 figure 18 : typical compensation network - + 13v osc comp source drain vdd u1 viper100 10 k w fc00220 figure 20 :external clock synchronization figure 21 :current limitation circuit example - + 13v osc comp source drain vdd viper100 u1 r1 r2 q1 fc00240 viper100/sp - viper100a/asp 15/20 t1 u1 viperxx0 13v osc comp source drain vdd - + 1 5 2 3 4 c4 c2 c5 c1 d2 r1 r2 d1 c7 c6 c3 iso1 from input diodes bridge to secondary filtering and load fc00500 figure 22 : recommended layout layout considerations some simple rules insure a correct running of switching power supplies. they may be classified into two categories: - to minimise power loops: the way the switched power current must be carefully analysed and the corresponding paths must present the smallest inner loop area as possible. this avoids radiated emc noises, conducted emc noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. - to use different tracks for low level signals and power ones. the interferences due to a mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (input overvoltages, output short circuits...). in case of viper, these rules apply as shown on figure 22. the loops c1-t1-u1, c5-d2-t1, c7-d1-t1 must be minimised. c6 must be as close as possible from t1. the signal components c2, iso1, c3 and c4 are using a dedicated track to be connected directly to the source of the device. viper100/sp - viper100a/asp 16/20 dim. mm inch min. typ. max. min. typ. max. a 4.30 4.80 0.169 0.189 c 1.17 1.37 0.046 0.054 d 2.40 2.80 0.094 0.110 e 0.35 0.55 0.014 0.022 f 0.60 0.80 0.024 0.031 g1 4.90 5.28 0.193 0.208 g2 7.42 7.82 0.292 0.308 h1 9.30 9.70 0.366 0.382 h2 10.40 0.409 h3 10.05 10.40 0.396 0.409 l 16.60 17.30 0.653 0.681 l1 14.60 15.22 0.575 0.599 l2 21.20 21.85 0.835 0.860 l3 22.20 22.82 0.874 0.898 l5 2.60 3.00 0.102 0.118 l6 15.10 15.80 0.594 0.622 l7 6.00 6.60 0.236 0.260 m 2.50 3.10 0.098 0.122 m1 7.56 8.16 0.298 0.321 r 0.50 0.020 v4 90 o 90 diam. 3.70 3.90 0.146 0.154 a c h2 h3 h1 l5 diam l2 l3 l6 l7 f g1 g2 l l1 d r m m1 e resin between leads v4 p023h3 pentawatt hv (vertical) mechanical data viper100/sp - viper100a/asp 17/20 dim. mm inch min. typ. max. min. typ. max. a 4.30 4.80 0.169 0.189 c 1.17 1.37 0.046 0.054 d 2.40 2.80 0.094 0.110 e 0.35 0.55 0.014 0.022 f 0.60 0.80 0.024 0.031 g1 4.90 5.28 0.193 0.208 g2 7.42 7.82 0.292 0.308 h1 9.30 9.70 0.366 0.382 h2 10.40 0.409 h3 10.05 10.40 0.396 0.409 l 16.42 17.42 0.646 0.686 l1 14.60 15.22 0.575 0.599 l3 20.52 21.52 0.808 0.847 l5 2.60 3.00 0.102 0.118 l6 15.10 15.80 0.594 0.622 l7 6.00 6.60 0.236 0.260 m 2.50 3.10 0.098 0.122 m1 5.00 5.70 0.197 0.224 r 0.50 0.020 v4 90 o 90 o diam. 3.70 3.90 0.146 0.154 a c h2 h3 h1 l5 diam l3 l6 l7 f g1 g2 l l1 d r m m1 e resin between leads v4 p023h2 pentawatt hv 022y(vertical high pitch) mechanical data viper100/sp - viper100a/asp 18/20 dim. mm inch min. typ. max. min. typ. max. a 3.35 3.65 0.132 0.144 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 c 0.35 0.55 0.013 0.022 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 1.27 0.050 e 9.30 9.50 0.366 0.374 e1 7.20 7.40 0.283 0.291 e2 7.20 7.60 0.283 0.300 e3 6.10 6.35 0.240 0.250 e4 5.90 6.10 0.232 0.240 f 1.25 1.35 0.049 0.053 h 0.50 0.002 h 13.80 14.40 0.543 0.567 l 1.20 1.80 0.047 0.071 q 1.70 0.067 a 0 o 8 o detail oao plane seating a l a1 f a1 h a d d1 == == == e4 0.10 a e1 e3 c q a == b b detail oao seating plane == == e2 6 10 5 1 eb he m 0.25 == == 0068039-c powerso-10 mechanical data viper100/sp - viper100a/asp 19/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com . viper100/sp - viper100a/asp 20/20 |
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